Various systems have been used in the prior art to generate timing signals necessary for the operation and testing of CMOS Dynamic Random Access Memories (DRAMs). Among these systems are those which generate leading and trailing pulse edges for strobing row and column addresses and control signals. In addition, various analog and digital delay lines and programmable cycle delays have been used. These devices generally restrict the critical signal edges to clock boundaries, or delay them such that time losses of the order of a clock cycle may occur.
Other systems are known which generate a signal that is propagated along a delay chain, with the propagated signal being sampled periodically, and stored in leading and trailing edge registers. In such embodiments, multiplying and rounding are required to generate the leading and trailing edges.
U.S. Pat. No. 3,162,815 issued to Mogensen discloses a sequential pulse generator with independently adjustable pulse width and spacing that employs combinatorial logic, flip-flops and adjustable delay lines with each pulse output on a separate line.
U.S. Pat. No. 3,840,815 issued to Masters discloses a programmable pulse width generator incorporating a master clock, binary counters, a self-incrementing pulse width control, and a pulse combination circuit used to add component pulses into a single pulse. Pulse width is adjusted in increments of the master clock period by applying a hold condition when the pulse width reaches the desired amount, thus stopping the internal counters. Timing resolution for the system is specified as 2 .mu.s (microsecond), which is not acceptable for DRAMs or SDRAMs typically having pulse widths of 10 to 30 nanoseconds.
U.S. Pat. No. 4,165,490 issued to Howe, Jr. et. al. discloses a clock pulse generator with adjustable pulse delay and pulse width control. A continuously running clock oscillator applies a stream of pulses to one or more adjustable-tap, coarse delay lines whose output in turn is applied to one or more finely adjustable delay lines. An additional "dither" delay is optionally added to provide further delay adjustment within half the time step of the preceeding delay lines. Selection of coarse, fine, and dither delay amounts, and selection of delay mode, is provided by a "latch ring" shift register.
U.S. Pat. No. 4,415,861 issued to Palmquist, et al discloses a programmable pulse generator wherein a trigger initiates a clocked sequential addressing of a pre-programmed high-speed memory from which stored 0's and 1's are read out as logic low and high levels. When the trailing edge is read out, the clocking is stopped and the addressing circuit is reset in preparation for the next trigger. An alternative embodiment creates a second pulse-generating section by duplicating the trigger and output circuits of the first pulse for the second pulse. The clocking, sequential addressing means, and pre-programmed high-speed memory are shared, and a second memory bit is read out. Either of the two programmable pulse sections may be independently or coincidentally triggered; however, because of the shared circuitry listed above, triggering of one section before the pulse in the other section has completed will result in an erroneous pulse.
U.S. Pat. No. 4,494,021 issued to Bell et al discloses a self-calibrated clock and timing signal generator for incorporation into MOS/VLSI circuitry. The disclosed circuit achieves self-calibration by creating a voltage-controlled oscillator (VCO) comprising five inverting voltage-controlled delay elements connected as a ring oscillator, and by incorporating the VCO in a phase-lock loop (PLL). When the PLL is locked to an externally supplied calibration reference frequency, and with the control voltage output of the phase detector of the PLL controlling the VCO also controlling a tapped delay line of identical inverting voltage-controlled delay elements, each element in the delay line has a delay equal to one-tenth of the period of the reference clock. The assumption made is that because both of the inverting voltage-controlled delay elements comprising the VCO are identical in construction and proximate to same elements of the delay line, voltage-to-delay characteristics of all such elements are nearly identical. This is a simple delay line with no capability for leading signal edge and trailing signal edge generation.
U.S. Pat. Nos. 5,208,598 and 5,224,129 issued to Lueker et al discloses a triggerable pulse generator incorporating a voltage-controlled oscillator (VCO). The oscillator generates pulses whose edge locations have a coarse location defined by the contents of a pre-programmed memory in increments of the VCO period. The increments are further refined by defined "slivers" in small digitally controlled increments, and defined "verniers" in yet smaller analog controlled increments. The resolution which is cited is 1 ps (picosecond). This system has no facility for dynamic alteration of pulse parameters, which is required in testing memory modules at their full operating speed.